In keeping up with the rapid progress in the IT (Information Technology), the data transmitting rate on e.g. a transmission channel is increasing incessantly. One of the indices for the quality for high rate data transmission is jitter. Among the factors responsible for degrading jitter characteristics, there is power supply noise in an input/output circuit and in an internal circuit. In a known manner, the power supply noise is increased by simultaneous operation of the plural input/output circuits and the internal circuit. Thus, various attempts were made for shifting the data transition timing with, e.g. a delay circuit.
For example, there is known an output circuit disclosed in Patent Document 1. This output circuit and a timing diagram therefore are shown in FIGS. 6 and 7, respectively. If plural simple output buffers are arrayed, and data signals I0 to In-1, entered to an output circuit, are of the same pattern and are of coincident transition point timings, data transition points of output signals Q0 to Qn-1 are also coincident, with a result that the transient current is increased and hence the power supply potential VCC as well as the ground potential is subjected to significant transient variations. In order to tackle with this inconvenience, even-numbered output buffers and odd-numbered output buffers in the embodiment of FIG. 6 are of different circuit configurations from each other so that the transition timings of the even-numbered and the odd-numbered output buffers are not coincident with each other. Specifically, as may be seen from the timings shown in FIG. 7, the even-numbered circuits are constructed for elongating the delay timing of the falling edge of the input signal, whereas the odd-numbered circuits are constructed for elongating the delay timing of the rising edge of the input signal. This offsets the timings of both the rising edges and falling edges of the even- and odd-numbered output signals, respectively, such as to distribute transient variations of the power supply voltage VCC and the ground potential VSS to suppress variations.
In the above Patent Document 1, the transition timings of the even-numbered output buffers are aligned to one another, whilst the transition timings of the output buffers of the odd-numbered are also aligned to one another. Hence, if desired to further suppress the variations (noise) of the power supply, it becomes necessary to control the output buffers independently of one another. The technique for implementing this has been shown in Patent Document 2. In the circuit shown in this Patent Document 2, the data signal and the control signal of one of two neighboring output buffers are entered as a control signal to the other output buffer to shift data transition timings of the totality of the output buffers automatically.    [Patent Document 1]
JP Patent Kokai Publication No. JP-A-3-290721 (FIGS. 1 and 3)    [Patent Document 2]
JP Patent Kokai Publication No. JP-A-11-27119 (FIG. 2)